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1/14 june 1998 ? AN627 application note serial eeprom compatible with plug-and-play vesa display data channel (versions 1.0 and 2.0) the st products whose names are of the form st24xy21 are application specific memory devices (asm). as well as containing 1 kb of eeprom, organized as 128 x 8, they are fully compatible with the vesa data display channel (vddc) modes, ddc1 and ddc2b. when installed in a plug-and-play pc display, the device can work in ddc1 mode, using only a 2 wire bus, or in both ddc1 and ddc2b modes, using a 3 wire bus. n ddc1: a unidirectional data channel from the display to the host pc, continuously transmitting extended display identification, edid, information. n ddc2b: a bidirectional data channel based on the i 2 c ? protocol. the host pc can request extended display identification information, edid, or video display interface information, vdif, over the ddc2b channel. in addition to this, the ddc2b channel can act as a transparent channel for access.bus ? communication, allowing the direct replacement to be made. table 1 summarizes the st24xy21 naming convention. those products whose names are of the form st24ly21 conform to version 1.0 of the vddc specification. those products whose names are of the form st24fy21 conform to the more recent (march 1996) version 2.0. those products whose names are of the form st24xc21 use the vclk line as the write control input, as described on page 7, and those of the form st24xw21 have a separate write control input. all st24xy21 devices are available in 8-pin pdip and so packages. figure 1 summarizes the pin-out for pdip. figure 1. st24xy21 pin connections (pdip) table 1. members of the st24xy21 family write control on vclk (pin 7) write control on pin 3 conformance to vddc version 2.0 st24fc21 st24fw21 conformance to vddc version 1.0 st24lc21b st24lw21 sda v ss scl vclk/wc nc nc v cc nc ai02409 st24lc21b 1 2 3 4 8 7 6 5 sda v ss scl vclk/wc nc nc v cc du ai02410 st24fc21 1 2 3 4 8 7 6 5 sda v ss scl vclk nc nc v cc wc ai02411 st24fw21 1 2 3 4 8 7 6 5 sda v ss scl vclk nc nc v cc wc ai02412 st24lw21 1 2 3 4 8 7 6 5
AN627 - application note 2/14 device description the functionality of the st24xy21 family greatly simplifies the design of the pc graphics board, and allows a direct connection between the display and the host pc using a standard video cable. each member of the family has a standard i 2 c interface, including the scl and sda lines, and an additional clock input, vclk, as required by the v.d.d.c. specification. this additional clock input allows the host pc to receive, from the display, all information required to configure the graphics board and the displays software driver. st24xy21 serial communication runs at 400 khz in both ddc1 and ddc2b modes, with a supply voltage between 3.6 v and 5.5 v. each member of the st24xy21 family operates in the two modes of the vddc specification. the transmit only mode of the st24xy21 corresponds to the ddc1 mode of the vddc, and the i 2 c bidirectional mode corresponds to the ddc2b mode. all members of the st24xy21 family power-up in ddc1 mode. the device w ill switch to the ddc2b mode upon the falling edge of the signal applied on scl pin. once in the ddc2b mode, the st24lc21b and st24lw21 cannot switch back to the ddc1 mode, except by first removing the power supply. however, the st24fc21 and st24fw21 enter a transition state after the falling edge of scl, during which the de- vice will switch back to the ddc1 mode if no valid i 2 c activity is observed. ddc1: transmit only mode figure 2 shows how, in the ddc1 mode, the st24xy21 uses the vclk input as a clock and the sda line for data output. the eeprom data are clocked out on the rising edge of vclk signal (pin 7). the scl input must be held high. figure 2. summary of the use of the st24xy21 in the dcc1 mode first, though, the device passes through an initial, internal, synchronization sequence, as depicted in figure 3. vclk is given nine free clock cycles, during which the sda pin is held in its high impedance state. on the rising edge of the tenth vclk pulse, the device starts to output, on the sda line, the data byte that is located at address 00h. this is transmitted serially, during the next nine clock cycles. the first eight cycles are used for transmitting the data bits themselves, with the most significant bit first. during the ninth cycle, the sda line is held in its high impedance state. this last bit, therefore, is readable as a logic 1 due to the pull-up resistor on the sda line. ai01707 scl v cc vclk sda v ss '1'
3/14 AN627 - application note figure 3. timing diagram for the ddc1 mode the internal address register is incremented automatically, and the data at the next location is transmitted during the next nine clock periods. this cycle continues indefinitely, so long as the scl line is held high, with the address wrapping round from 7fh (the 127th byte) back to 00h. unlike the ddc2b mode, the ddc1 mode does not provide for the issuing of instructions or commands to the memory, and does not provide for the writing of data. the detection of a logic 0 for the ninth bit indicates that the memory has lost synchronization, and that the data are no longer valid. it is then necessary to re-synchronize the communication by turning off the power to the memory, and then back on again, or by checking the synchronization block of data written in the st24xy21 device. ai01501 bit 7 v cc tvpu scl sda vclk bit 6 bit 7 v cc scl sda vclk bit 6 bit 6 bit 4 bit 0 12 891011 12 13 17 18 19 20 bit 5
AN627 - application note 4/14 ddc2b: i 2 c bidirectional mode the i 2 c standard two-wire serial interface includes a bidirectional data line (sda) and a serial clock (scl), as indicated in figure 4. in addition, the whole st24xxx and st25xxx family offers a write control feature, as described in application notes an404 and an1006. for the st24xy21 family, this is appears as described in the following list: n when the st24lc21b or st24fc21 is in the ddc2b mode, the vclk input (pin 7) acts as the write enable/disable control. C when vclk = 1, write instructions are permitted C when vclk = 0, write instructions are ignored. n when the st24lw21 or st24fw21 is in the ddc2b mode, the write control input (wc), pin 3, acts as the write enable/disable control. C when wc = 1, write instructions are permitted C when wc = 0, write instructions are ignored. figure 4. summary of the use of the st24xy21 in the dcc2b mode ai02408 scl v cc wc sda v ss '1' = write enable '0' = write disable
5/14 AN627 - application note the st24xy21 is switched from the ddc1 mode to the ddc2b mode by taking the scl pin low, as indi- cated in figure 5. figure 5. timing for the transition from ddc1 mode to ddc2b mode the st24xy21 takes the role of the slave device in the i 2 c protocol, with all memory operations synchro- nized by the serial clock, scl. the vclk input (pin 7) is ignored during read accesses, but for the st24fc21 and st24lc21b, it has an effect on write accesses, as described on page 7. table 2 shows that all read and write operations are initiated by a start condition generated by the bus master. the start condition is followed by a stream of 7 device select bits (transmitted with the most significant bit first), plus one read/write bit, and is terminated by an acknowledge bit. 1. x = dont care = vih or vil table 2. device operations mode r/w bit st24lc21b st24fc21 vclk/wc 1 st24lw21 st24fw21 wc 1 bytes initial sequence current address read 1 x x 1 start, device select, rw = 1 random address read 0 x x 1 start, device select, rw = 0, address 1 x x restart, device select, rw = 1 sequential read 1 x x 3 1 similar to current or random read byte write 0 vih vih 1 start, device select, rw = 0 page write 0 vih vih 8 start, device select, rw = 0 ai01892 scl sda vclk transmit only mode 1 2 89 msb ack start condition - temporary bi-directional mode (st24fc21 and st24fw21) - locked bi-directional mode (st24lc21b and st24lw21) - locked bi-directional mode (st24fc21 and st24fw21)
AN627 - application note 6/14 table 3 shows how the stream of 7 device select bits is composed of the 4 bit device select code (built- in with the value 1010) followed by 3 dont care bits (x indicating that the bit can be either 0 or 1). when the bus master writes data to the memory, the st24xy21 responds to the eight received data bits by asserting an acknowledge bit during the 9th bit time. when data is read by the bus master, it must ac- knowledge the receipt of the data bytes in the same way. data transfers are terminated with a stop con- dition (as described in descriptions of the read and write sequences in the st24xy21 data sheet). table 3. device select code in the ddc2b mode device code chip enable rw bit b7 b6 b5 b4 b3 b2 b1 b0 device select 1010xxxrw
7/14 AN627 - application note control of the write operation hardware control of the write operation, using the wc input, is a useful facility for protecting the contents of the memory from inadvertent erase/write cycles (in the ddc2b mode). not only does the device ignore the write operation if wc is not high at the start of the operation, but it aborts the operation if wc ceases to be held high, perhaps because of a noise glitch on the wc line. that is, the device errs on the side of safety, and protects itself against writing if there is any question as to the validity of the incoming data. the availability of the wc input is summarized in table 4. writing is enabled when wc is held at vih, and disabled when it is held at vil. figure 6 shows the timing of the byte-write and page-write operations, and shows how the level on the wc input must be taken high before commencing the start condition, and must be held high until after the stop condition has finished. figure 6. timing sequence of write operations (wc = 1) table 4. availability of the write control input st24fc21 st24lc21b st24fw21 st24lw21 ddc2b, i 2 c bidirectional mode pin 7 = wc pin 7 = dont care pin 3 = wc ddc1, transmit only mode pin 7 = vclk pin 7 = vclk pin 3 = dont care stop start byte write dev sel byte addr data in start page write dev sel byte addr data in 1 data in 2 ai02413 stop data in n ack ack ack r/w ack ack ack r/w ack ack wc wc
AN627 - application note 8/14 write operations are ignored when wc is taken low, as depicted in figure 7. however, the timing remains the same, with nine clock cycles per data byte, including an acknowledge bit at the end of each. figure 7. timing sequence of inhibited write operations (wc = 0) because the device is designed to abort from a write operation if there is any question as to the validity of the incoming data, it is recommended that the status of the write operation be checked at completion. the algorithm in figure 8 shows an algorithm in which a test is made at the start of the write operation, to check that device has been correctly initiated. if the memory sends back the acknowledge after the first loop, no write cycle is in progress. this means that either the write sequence was corrupted by glitches or the signal applied on wc was not stable at vih during the write sequence. this ack polling algorithm must be used just after the write sequence because the memory will not send back the acknowledge while the internal write cycle is in progress. stop start byte write control byte byte adrs data start page write byte adrs n data n data n + 1 ai02414 ack ack ack ack ack ack wc control byte data n + 7 stop ack ack
9/14 AN627 - application note figure 8. the ack polling algorithm (to check that the write cycle has started correctly) error recovery modes (available on st24fc21 and st24fw21) when the st24fc21 or st24fw21 first switches to the ddc2b mode, it enters a transition state, as shown in figure 9. if the device does not receive a valid i 2 c sequence, that is a start condition followed by a valid device select code (1010xxx rw), within either 128 vclk periods or a period of time of trecovery (approx- imately 2 seconds), the device will return to the ddc1 mode. whenever there is a high to low transition on the scl input, the counter of the vclk line and the trecovery watchdog timer are both reset. if more than 128 vclk pulses or trecovery elapses between successive high to low transitions of scl, the device returns to the ddc1 mode. if, though, the device receives a valid i 2 c sequence, it locks itself in the ddc2b mode. write cycle in progress ai01099b next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop proceed write operation proceed random address read operation send byte address first byte of instruction with rw = 0 already decoded by st24xxx
AN627 - application note 10/14 figure 9. error recovery mechanism flowchart (for the st24fc21 and st24fw21) ai01748 switch back to transmit-only mode memory power on internal address pointer = 0 vclk yes no no send data bit (msb first) pointed by the address pointer and auto-increment pointed bit/byte scl yes no sda hi-z vclk internal counter = 0 start internal 2 sec timer scl yes reset vclk internal counter and reset internal timer valid i 2 c access (start + device select) ? yes vclk yes increment vclk counter counter = 128 or timer > 2 sec yes i 2 c communication idle waiting for a device select byte reset counter and timer send acknowledge respond to the incoming i 2 c command transition state (vesa 2) transmit-only mode (ddc1) i 2 c mode (ddc2b) no no
11/14 AN627 - application note typical application schematic the st24xy21 is used in a plug-and-play pc display to transmit all the display information needed by the host pc in the ddc1 and ddc2b modes. in particular, during the pc boot-up and configuration process, the system software interrogates the display as to its capabilities and operating parameters. the physical specification for the connector, between the display and the host pc graphics controller, is backward compatible to that of the standard 15-pin, vga-type, connector. the pin-out of the vga con- nector is described in table 5. this shows how the host pc and the display connections vary, depending on the vddc standard available in the host pc graphics controller. according to version 2.0 of the vesa data display channel specification, the host pc graphics controller board needs to provide a 2.2 k w pull-up resistor on the bidirectional data line (sda), and on the data clock line (scl), to ensure correct switching between the ddc1 and ddc2b modes. the display pcb board also needs to provide a 47 k w pull-up resistor on the data clock line (scl). table 5. 15-pin vga connector pin-out description pin standard vga ddc1 host pc ddc2b host pc ddc1/2b display 1 red video red video red video red video 2 green video green video green video green video 3 blue video blue video blue video blue video 4 display id bit 2 display id bit 2 display id bit 2 optional 5 test (ground) return return return 6 red video return red video return red video return red video return 7 green video return green video return green video return green video return 8 blue video return blue video return blue video return blue video return 9 no connection (mechanical key) 5 v supply 5 v supply 5 v supply 10 sync return sync return sync return sync return 11 display id bit 0 display id bit 0 display id bit 0 optional 12 display id bit 1 data from display bidirectional data (sda) bidirectional data (sda) 13 horizontal sync horizontal sync horizontal sync horizontal sync 14 vertical sync vertical sync (vclk output) vertical sync vertical sync (vclk output) 15 display id bit 3 display id bit 3 data clock (scl) data clock (scl)
AN627 - application note 12/14 figure 10 depicts a typical pc display application schematic using a member of the st24xy21 family. the ddc1 clock signal, vclk, is connected to pin 14 of the vga connector. the data clock line, scl, used for the ddc2b mode, is connected to pin 15 and the bi-directional data line, sda, is connected to pin 12. figure 10. schematic of a typical pc display application for the vesa 2.0 specification, a +5v supply voltage generated by the host pc is available on the pin 9 of the vga connector (used for the acc ess.bus protocol). this +5 v supply volt age may be used to sup- ply the vcc voltage of the st24xy21. this allows a proper power-up sequence, driven only by the host pc. if the host pc and the display are powered-on asynchronously, the first to come on will power the st24xy21 inside the display. the scl (the ddc2b clock) and sda (data) pins of the st24xy21 can be directly connected to the vga connector. an esda6v1 transil array may be used in order to improve the memory protection against electrostatic discharge (esd) and latch-up. diode protection is advisable on the signals that connect directly between the st24xy21 and the external vga connector. however, it is not necessary to provide external protection against slow rise and fall times or bounces, since the members of the st24xy21 already contain ttl-compatible schmitt-triggers on these inputs. ai01891 1-8, 10, 11, 13 14. vert sync 15. data clock 12. bi-directional data 9. 5v supply vga connector vsync video module + tht controller +5v 47k w scl sda v cc vclk v ss st24lc21 1 15
13/14 AN627 - application note power supply voltage in the vesa 2.0 specification according to the vesa 2.0 specification, the st24xy21 can be s upplied by either the display or by the host pc power supply (using the +5 v line, pin 9, on the vga cable). the easiest way to implement this is to use two diodes, as shown in figure 10. the st24xy21 supply voltage is decreased by the diode forward voltage drop (about 0.6 v) and hence below 4.5 v. nevertheless, the st24xy21 remains operational, and no input will be damaged if the applied voltage on each input complies with the absolute maximum ratings values. however, the threshold volt- age of the schmitt-trigger (pin 7) needs to be decreased in this case (as described in the st24xy21 data sheet).
AN627 - application note 14/14 if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail address: apps.eeprom@st.com please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 1998 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapor e - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a.

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